The complexity, size, and typically the power of an analog-to-digital converter increases with the resolution of conversion result required. Typically the minimum and maximum input signals are mapped onto the span of the converter. However, in many applications the input signal may have a short-term variation which covers a subset of the converter span. The resolution required is calculated over the full span, but if you focus on the sub-span a much lower resolution is adequate. Another way of looking at the problem is that a large portion of the span is unused for most of the time. The result is that for most of the time the converter used has excess resolution, with a more complex and costly circuit.
One solution is to use a converter with a lower span, with sufficient resolution and span to cover the short-term signal variations. Typically the output of an offsetting DAC is subtracted from the input signal to the ADC, so as to remove any large offsets and keep the signal within the reduced span. Such approaches use a DAC to subtract an offset from the input signal for the ADC. However, they do not automatically update the DAC in response to the ADC signal going outside range. Instead, they are simply set to a fixed offset by a host micro, typically after a calibration cycle or offset nulling procedure. They do not adaptively set the DAC to keep the ADC input within range, nor do they teach this approach. Therefore they do not teach any methods of automatic correction of the ADC output codes to take the DAC change into account.
It is common practice to process the output signal from sensors, an analog signal, using microprocessors or similar digital signal processing devices. The analog signal is translated into the digital domain by an analog-to-digital converter (ADC). An ADC is what is termed a mixed-signal device in that it contains both analog and digital circuitry. The ADC converts the analog signal into a digital word of a given number of bits, N. The ADC will have 2N steps. The span of the ADC is the difference between the minimum and maximum voltages that can be applied to the input, i.e. the voltages that give an ADC output of the smallest and largest digital word for number of bits N. Taking the example that, N is 16, so the smallest digital word is 0000h (0 decimal) and the largest is FFFFh (65535 decimal), corresponding to input voltages of 0V and 4V, respectively, then the step size of the ADC, its resolution, is given as the span divided by the number of digital steps, i.e. (SPAN/2N). In this example the resolution is 61 uV. This means that the ADC can only measure steps of more than 61 uV; an input change of smaller than this amount might not result in a change of the digital output word.
The design of an ADC typically becomes exponentially more difficult as the number of bits N increases. The analog circuitry in the ADC becomes larger, more complex and requires more power. By comparison, the digital circuitry will become larger but marginally more difficult; extra digital processing is relatively easily added. In many cases the signal being digitized is slowly varying, and this slow variation is being measured. For example assume the signal being measured has a range from 0v to 4v, but might have a much lower variation for successive measurement points. If we assume that the maximum variation for successive measurements is known to be no more than say 0.1v, then at any given time most of the full converter span is not being used. If we reduce the span from 4V to 0.25V we can achieve the 61 uV ADC step size with an ADC with a 12-bit digital output word (N=12), and not require the 16-bit design. Per the earlier comments, the design of a 12-bit ADC is significantly easier, smaller, and lower power than a 16-bit ADC, all other parameters being equal. The required ADC step size could be obtained with a 12-bit ADC working on a 0.25V sub-span of the full 0 to 4V range. However, it is necessary to be able to adjust the location of the 0.25V sub-span across the full range; a fixed sub-span of 0 to 0.25V will not meet the objective. A commonly used approach is to use a DAC to subtract a voltage from the input signal. There are several examples of ADC systems with this architecture. In all such cases the DAC is typically set once when configuring and/or calibrating the system, and is not normally changed by the converter itself. The DAC setting is typically written to the part by a microprocessor. The DAC is not set in a stand-alone fashion, a host controller is required.